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HEWLETT-PACKARD JOURNAL Technical Information from the Laboratories of Hewlett-Packard Company

MAY 1980 Volume 31 • Number 5

Contents: A Programmable Selective Level Meter (Wave Analyzer) with Synthesized Tuning, Autoranging, and Automatic Calibration, by Paul L Thomas It's useful in audio, sonar, radio, and frequency division multiplex systems testing. Precision Synthesizer/Level Generator Has High Spectral Purity for Telecommunica tions Testing, by Phillip D. Winslow A powerful complement to a selective level meter, it's also a precision general-purpose signal source. A Monolithic Thermal Converter, by Peter M. O'Neill Integrated circuit technology pro duces a converter. broadband, monolithic silicon thermal rms-to-dc converter. Increased Versatility for a Versatile Logic State Analyzer, by Justin S. Morrill, Jr. and John D. Hansen Now it can capture microprocessor events at different times and places and dis play them all together. General-Purpose Module Adapts Dedicated Logic State Analyzer to Almost Any Microprocessor, by Deborah J. Ogden Personality modules customize this analyzer for test ing particular microprocessors. This new module isn't so particular.

In this Issue: Our cover photo shows two of this month's featured products doing one of their principal jobs, testing telephone equipment. A frequency division multiplex (FDM) telephone system like the range on the cover carries many telephone channels, each spanning a frequency range of 0 to composite Hz, stacked one on top of another in frequency. Thus the composite signal trans mitted energy point to point over microwave radio links is a broadband signal with its energy 'I spread out over a wide range of frequencies. In testing a system like this, it's often necessary " "a to channel. how much energy is in one particular channel or part of a channel. That's the job i ) of a the level meter like Model 3586A/B/C (page 3). It selects the narrow band of fre quencies narrow user wants to measure, and then itmefers the signal level (the amount of energy) in that narrow band. Sometimes it's useful to send a precise tone over a channel and measure what happens to it with a selective level meter. Generating that tone with a precise frequency and magnitude is the job of Model 3336A/B/C Synthesizer/Level Generator (page 9). The A and B versions of the 3586A/B/C and 3336A/B/C are designed uses for telephone testing in Europe and North America. And since there are many other uses for such instruments besides telephone testing, there's a C version of each one for general-purpose design, manufacturing and maintenance applications. (We're grateful to Southern Pacific Communications Company for allowing us to use their FDM equipment as a backdrop for our cover photo.) Rounding for this month's issue are two logic state analyzer articles. Logic state analyzers are used for checking information flow in digital systems such as computers and microprocessors. Model 1610A has been Hewlett-Packard's most capable general-purpose logic state analyzer. Now there's a new version, Model 161 OB, microprocessors, the more flexibility in how data is captured (page 14). For example, in some microprocessors, the addresses of memory locations and the data stored in those locations appear on the same bus, but at different times. side. 161 OB can catch them both and display them side by side. Model 1 microprocessors. customize it Logic State Analyzer is designed specifically for testing microprocessors. You can customize it to test Several modules microprocessor by plugging in a personality module. Several personality modules are available, one for each of the more widely used microprocessors. Unlike these, the latest module, Option 001 , isn't the for any particular microprocessor, but instead turns the 1611 A into a general-purpose micro processor analyzer. This story starts on page 19. -R. P. Do/an Editor, Richard P Dolan • Contributing Editor, Howard L Roberts • Art Director, Photographer. Arvid A. Danielson Illustrator, Nancy S Vanderbloom • Administrative Services, Typography, Anne S. LoPresti • European Production Manager, Dick Leeksma

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A Programmable Selective Level Meter (Wave Analyzer) with Synthesized Tuning, Autoranging, and Automatic Calibration Covering an input frequency range of 50 Hz to 32.5 MHz, this tuned voltmeter measures characteristics of both the voice channels and the multiplexed channels of FDM communications systems. An alternate version functions as a general-purpose wave analyzer. by Paul L Thomas

INSTRUMENTS THAT CAN TUNE OUT all but one frequency component in a complex signal and measure the component's amplitude precisely are known as selective level meters or wave analyzers — terms that have practically become synonymous. If there has been any difference between a wave analyzer and a selective level meter (SLM) it is that the SLM is optimized with the appropriate bandwidths and input im pedance levels for telephone system measurements while the wave analyzer is designed for general-purpose use on all kinds of signals. The SLM is designed to select and measure a particular telephone channel or pilot tone in an FDM (frequency division multiplexed) communications

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Spectrum analyzers, another kind of instrument, also separate the frequency components of a signal for analysis, but since they display all components within a selected frequency range at the same time, they are designed for wide dynamic display range and therefore have more diffi culty in achieving the amplitude measurement accuracy that SLM/wave analyzers are capable of achieving. *A fundamental difference between wave and spectrum analyzers is in the shapes of the filter response Spectrum analyzers need filters with Gaussian-shaped response so the filters wave ring as the tuning sweeps a signal through the filter's passband. A wave analyzer's filters, on the other hand, can have steeper skirts since the signal usually remains in the passband long enough for transients to settle down, and the top of the response curve s flattened to allow for a slight amount of mistunlng.

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Fig. 1. Model 3586A/B/C Selec tive Level Meter (3586C shown) is designed for general-purpose wave analysis and telecommuni cations applications including au dio, sonar, radio, and frequency division multiplex (FDM) systems testing. It has a frequency range of 50 Hz to 32.5 MHz, ±0.2-dB level accuracy, and 0.1 -Hz frequency resolution.

MAY 1980 HEWLETT-PACKARD JOURNAL 3

© Copr. 1949-1998 Hewlett-Packard Co.

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Fig. differ configurations B, and C versions of the 3586 Selective Level Meter differ in their input configurations and internal filters. Model 3586 A meets CCITT requirements; Model 3586B is for North American (Bell) analysis. and Model 3586C is for general-purpose wave analysis.

Hewlett-Packard has been designing and manufacturing wave analyzers for years, some of which (the 312C and 312D) are optimized for telephone applications. New SLMs and wave analyzers are now being designed around mi croprocessors to achieve greatly enhanced capabilities. The first of the new microprocessor-controlled generation of SLMs was the Model 3745A Selective Level Measuring Set,1 introduced in 1975. This instrument greatly reduces the time needed to tune to a particular channel or pilot tone in an FDM system by having tables of the 3600 or so FDM frequencies stored in read-only memory (ROM). The operator tunes the instrument to the proper frequency sim ply by entering a description of the desired channel (chan nel number, group number, supergroup number, etc.) by way of the keyboard. The microprocessor looks up the cor rect frequency for the selected measurement on that chan nel and then, by control of the synthesized first local oscil lator, tunes the analyzer accordingly. This plus autoranging greatly speeds measurements of gain, loss, noise, and other characteristics of telephone systems. It also enables the instrument to be readily incorporated into automatic sys tems. A lower-cost microprocessor-controlled SLM has now been designed for use in laboratory, production test, and system maintenance applications. This one, Model 3586A/B/C (Fig. 1), is tuned manually, but as we shall see, microprocessor control simplifies its tuning and gives it other convenience features such as full remote control through the HP interface bus (HP-IB). An Overview

The new Model 3586A/B/C Selective Level Meter has a frequency range of 50 Hz to 32.5 MHz, covering both the telephone voice band and multiplexed channel frequen cies. * * The user may thus compare measurements made on the same channel at both the voice-frequency and multi plexed levels. A synthesized local oscillator makes it pos'Compatible with ANSI/IEEE 488-1978 **The instrument is usable down to 10 Hz with unspecified performance

sible to set the frequency tuning with 0.1 -Hz resolution. A built-in counter measures the frequency of an unknown signal accurately so the instrument can be tuned exactly to that frequency without the necessity to spend time "rock ing" the tuning control to center the signal in the instru ment's passband. The amplitude measurement range is from +25 to -125 dBm with errors less than ±0.2 dB over the major part of the instrument's input range. Autoranging permits use of a 10-dB display range, giving an amplitude measurement resolution of 0.01 dB for examining the fine-grain fre quency response of telephone channels. The microprocessor scales the measured quantity so re sults are displayed in the units selected (dBm, dBpW, or dBV referred to 0.775V). A reference reading may be stored as an offset by use of the RDNG-»OFFSET key so relative measurements may be made, for example, with respect to the test level point (TLP) or the fundamental frequency component of a signal. Any other reference value may also be stored as an offset using the numeric keypad. Automatic calibration to an internal standard every three minutes and use of a true-rms detector assure accuracy in both tone and noise measurements. The instrument can also measure the total power in broadband signals applied to its input, giving a quick indication of the power level of a multiplexed signal. To meet the requirements of a broad range of applica tions, several input configurations are provided. Model 3586A, intended for use in CCITT-compatible telephone systems, has a 75O/10kfi single-ended input using a BNC connector, and 150Ã1 and 600Ã1 balanced inputs using Siemens 3-prong connectors (Fig. 2). These input config urations are suitable for connecting the instrument to vari ous levels within the FDM hierarchy. Model 3586B, for Bell-compatible systems, has a 75ÃI single-ended input and 124Ã1, 135Ã1, and 600Ãà balanced inputs with appropriate WECO connectors. Model 3586C, intended for general-purpose waveanalyzer applications, has a single-ended 50fi/75fi input

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© Copr. 1949-1998 Hewlett-Packard Co.

0-32.5 MHz

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Fig. receiver. bandwidth 3586A/B/C is a dual-conversion superheterodyne receiver. Resolution bandwidth is determined by the second-IF filters.

using a BNC connector, and a 600fi balanced input using a dual-banana connector. Other impedance-connector combinations are available for any of the versions. All provide probe power at the front panel for wideband, high-impedance, active probes. Filter bandwidths of 20 Hz and 400 Hz are standard on all versions, and 3100 Hz is optional. Model 3586A (CCITTJ also includes a 1740-Hz psophometric equivalent noiseweighting filter, and Model 3586B (Bell) includes a 2000Hz C-message equivalent noise-weighting filter so mea surements made with these instruments can be related to traditional noise measurements on telephone systems. The transmission impairments measurement option includes a highly selective 3100-Hz channel filter plus a true psophometric or C-message noise weighting filter for more accurate noise level measurements. With this option, the telephone-oriented versions can make transmission im pairment measurements such as noise-with-tone, signalto-noise-with-tone ratio, phase jitter, and single-level im pulse noise. Because of their extended frequency range, the instruments are capable of making these measurements at the multiplex level as well as at voice frequencies. All versions also work with the Model 3336A/B/C Synthesizer/Level Generator (see page 9). This instrument generates sine waves with accurately-controlled amplitude levels. Its tuning can be controlled by the 3586A/B/C SLM through the HP Interface Bus to function as a tracking signal source for measurements made with the 3586A/B/C. The 3586A/B/C SLM itself has a tracking output, useful for fre quency-response measurements but lacking the level settability of the 3336A/B/C. Semiautomated Tuning

To tune the 3586A/B/C, the operator enters the desired frequency through the numeric keyboard. To change the tuning, the operator can enter a new number or use the up-down step keys or the rotary tuning knob. The amount by which the step keys and tuning knob change the fre quency can be selected with 0.1-Hz resolution by entering the desired step value through the numeric keypad and pressing the FREQ STEP key. One can enter the frequency being measured as the frequency step, for example, and then step from harmonic to harmonic, or enlei 4 kHz anu step from one channel of an FDM signal to the next. When measurements are being made on multiplexed telephone channels, the user need only enter the carrier frequency for that channel, then indicate whether the chan

nel signal is in the upper or lower sideband, using the /I (upper) or |~\ (lower) key. The instrument's tuning is automatically offset the exact 1850 Hz needed to center the tuning in the selected sideband. Other keys can be used to offset the tuning to center the tuning on the channel test tones (800/1010 Hz for CCITT, 1004/2600 Hz for Bell). In each case it is not necessary to enter a nine-digit number to change the frequency — simply pressing the appropriate key changes the tuning by the required amount, saving much time in evaluating the performance of an FDM system. Tuning the instrument to a signal whose frequency is not known exactly is easily done by tuning the instrument approximately by any of the procedures just described and then pressing the COUNTER button. The counter will mea sure the largest signal within the selected bandwidth. Pressing the CNTR-»FREQ button then tunes the analyzer to the displayed counter frequency. Level Measurements Measurements of signal level have also been made easier with microprocessor control of autoranging. As with any wave or spectrum analyzer, the 3586A/B/C has a broadband input 3, as indicated in the block diagram of Fig. 3, whose purpose is to reduce the signal input to a level that assures that the largest signal component does not over drive or damage the input amplifier and mixer. The control for this attenuator on other analyzers is usually labeled INPUT SENSITIVITY, REFERENCE LEVEL, or MAXIMUM INPUT LEVEL. Then there is an IF gain control, usually called RANGE, that adjusts the IF gain to bring the selected signal component up to a suitable level for the detector. Obviously there are many combinations of the settings for these two controls that will bring the selected signal component up to a suitable detector level. For highest accuracy, however, the best combination is the one that uses the least attenuation at the input. The 3586A/B/C has a broadband rms detector at the input that senses the input level and sends this information to the microprocessor. The microprocessor then selects one of the eleven input attenuator steps accordingly. The micro processor is also sent the IF signal level sensed by the IF detector, and uses this information to select one of the * The SLM value is considered a better overload indicator lor an SLM than the peak or average value, each the many frequency components ol a multiplexed telephone signal, each ol which vectorially to is several dB below the composite power level, could add up vectorially to high peak values at random limes. The rms value permits the input attenuator to be set to a more operation range. The occasional overload peaks do not affect operation of the Model 3586A/B/C significantly

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© Copr. 1949-1998 Hewlett-Packard Co.

Fig. 4. Crystals in the 1st IF filter are stagger-tuned to achieve the desired bandwidth. However, at 49.96875 MHz, the cur rents through the shunt capacitances of the two crystals are exactly equal and of opposite phase, cancelling at point A to give a transmission zero at 49.96875 MHz.

eighteen gain steps to place the IF signal level within the detector's most linear 10-dB range. This assures maximum accuracy in the measurements. The user may, however, freeze either the input attenuator and/or the IF gain at any selected level for special measurement situations, such as scanning a spectrum to observe relative levels, or when using another instrument to make transmission impairment measurements on the demodulated output {the appropriate carrier may be reinserted to demodulate a channel for further analysis).

The 20-Hz filter (20 Hz at the 3-dB points) has a Butterworth shape and is flat within ±0.3 dB in the 6-Hz central portion of the response curve so a minor amount of frequency insta bility can be tolerated in the measured signal. The filter suppresses tones 80 Hz above and below the center fre quency by more than 50 dB. Hence, the filter can suppress a carrier at 104.00 kHz while passing a pilot at 104.08 kHz for measurement. The 400-Hz filter, a traditional value in selective level meters, responds faster than the 20-Hz filter so is useful when searching for a signal. The 1740-Hz (CCITT) and 2000-Hz (Bell) filters are simi lar to those used for many years in the measurement of equivalent noise in a telephone channel. These filters are centered at 1350 and 1500 Hz, respectively, from the lower end of the channel, so that their passbands begin at or near 500 Hz, an important area for voice fidelity. The 3100-Hz filter — standard in the 3586C, an optional replacement for the 1 740-Hz or 2000-Hz filter in the 3586A/B— is centered at 1850 Hz. This filter simulates an actual multiplexed chan nel filter. It has extremely steep response slopes (Fig. 5),

Two Conversions

As shown in the block diagram of Fig. 3, the 3586A/B/C is a dual-conversion, superheterodyne receiver. The first con version up-converts the input signal to an intermediate frequency of 50 MHz. This up-conversion places the image frequencies in a range of 100 to 132.5 MHz where they are easily suppressed by low-pass filtering. The final IF frequency is 15.625 kHz. In the traditional analyzer, a down-conversion from 50 MHz to 15 kHz would be accomplished in two or three down-conversion steps so that adequate separation can be maintained between the IF and its image at each down-conversion. However, minimiz ing the number of down-conversions is desirable because each down-conversion inevitably introduces some noise, phase instabilities, and harmonic distortion. Although in dividually these can be held to very low levels, the total obtained with several down-conversions may not be insig nificant, not to mention the cost of an additional local oscillator and mixer for each conversion. In the 3586A/B/C, down-conversion from the first IF to the final IF is accomplished in only one step. This was made possible by the use of a special type of filter for the first IF. Similar to a filter used in the Model 3571A Tracking Spec trum Analyzer,2 this filter, diagrammed in Fig. 4, passes the 50-MHz first IF signal with little insertion loss, but it has a sharp null at 49.96875 MHz where the image frequency lies. Two filters in cascade suppress the image by greater than 80 dB. The second IF filters provide the resolution bandwidth. *A frequency in this range was chosen because of the availability of suitable crystals for the bandpass filters The specific value was chosen because a carrier reference signal of 15 625 digital is obtained from a 1-MHz reference simply by use of a -i-64 digital 1C.

6 HEWLETT-PACKARD JOURNAL MAY 1980

© Copr. 1949-1998 Hewlett-Packard Co.

Fig. 5. Optional 3100 Hz filter simulates a multiplexed chan nel filter. It provides a flat response over ±1000 Hz and has high selectivity. These photos demonstrate its flatness, carrier rejection (-76.3 dB at 1850 Hz offset, and adjacent channel rejection (>80 dB).

giving the filter a shape factor of 1.2 (ratio of response curve width at -60 dB to width at -3 dB). The first cusp of all three filters lies exactly at the carrier frequency (±1350. ±1500. or ±1850 Hz from the center), thus suppressing any carrier leak. In the 3586A B. the noise filters included with this option are weighted according to the CCITT psophometric curve or the Bell C-message curve. Quiet, Precise Local Oscillator

A key element in any wave or spectrum analyzer is the first local oscillator. Any noise or frequency instability in this oscillator becomes impressed upon the input signal during the first frequency conversion. The 3586A/B/C uses a synthesizer as the first local oscillator, thus obtaining fre quency accuracy and stability. Exceptionally low noise and low spurious are achieved by use of the fractional-N technique,3 which provides nine-digit frequency resolution with only three phase-locked loops in the synthesizer. A block diagram of the synthesizer is shown in Fig. 6. The 50-to-82. 5-MHz first LO signal, f0, is taken from the voltage-controlled oscillator (VCO) in the summing loop. This oscillator is locked to both the step-loop and the fineloop frequencies, fs and ff respectively. The VCO in the step loop operates within a frequency range of 54 to 86 MHz. Its output, fs, is divided down in MECL circuits to 2 MHz by a factor N, where N is an integer between 27 and 43. The 2-MHz divided-down step loop output is compared to a 2-MHz reference in a phase com parator to derive a control signal that locks the VCO such that fs/N=2 MHz. Note that this is equivalent to multiply ing the 2-MHz reference by a factor N and that the phase noise multiplication factor increases by only 20 Iog10 (43/ 27), ~ 4 dB across the entire range. Phase noise is only about — 1 1 8 dBc/Hz anywhere in the instrument's frequency range. This is important in a highly selective SLM because phase noise in the local oscillator becomes impressed on the signal and has the effect of broadening the filter passbands. The 3586A/B/C's phase noise is low enough that even a large tone in an adjacent channel will be suppressed by more than 80 dB with the 3100-Hz filter (10 Iog10 3100 118 = -83 dB). The fine-loop frequency originates in a fractional-N loop similar to the one used in the Model 3336A Synthesizer/ Level Generator (see page 9). This loop generates a fre 10- M Hz Step Loop Reference

quency in the range of 20 to 40 MHz with eight-digit resolu tion. It is divided by 10 to obtain a signal, ff, in a range of 2 to 4 MHz that is compared in a phase detector to the differ ence between f0 and fs, the output and step-loop fre quencies. The output of the phase detector thus locks the summing-loop VCO such that the output frequency. f0. equals fs— ff. the difference between the step-loop and fineloop frequencies. To obtain nine-digit resolution without the fractional-N technique, more loops would have been required with a consequent increase in the quantity of spurious mixing products, as well as in cost. Wideband Rms Detector

For accuracy in making measurements on the complex signals encountered in communications systems, it was considered desirable to use a detector that responds to the rms value of the measured waveform. The requirement of an 80-dB dynamic range ruled out thermocouples and a number of other rms detectors. A commercially available 1C rms-to-dc converter was found that has desirable proper ties, such as low cost and both log and linear outputs, but a range of only 40 dB. It was therefore decided to devise a circuit that would compress an 80-dB signal range to 40 dB, and then adjust the display reading accordingly. A simplified diagram of the circuit is shown in Fig. 7. The input goes to an operational amplifier. The output of the amplifier is applied to the rms-to-dc converter, and the resulting dc current is coupled back to the input of the operational amplifier. The output of this amplifier thus has two components: an ac component, e0, that results from the signal input, and a dc output, V0, that results from conversion of the signal's rms value to dc. The dc component is applied to an integrator that drives a light-emitting diode. The diode in turn illuminates a photoresistor, RF, in the feedback loop of the input opera tional amplifier, adjusting Rp to maintain the dc voltage drop through Rp constant such that V0 is always equal to VR at the input to the integrator. RF, and hence the gain of the operational amplifier, varies inversely with the rms signal level, making e0 proportional to the square root of e¡, the input voltage. Thus an 80-dB input range is com pressed to 40 dB at the input to the rms-to-dc converter. The same type of rms-to-dc converter 1C is used for the

Summing Loop

Fig. 6. The first local oscillator synthesizer provides nine-digit frequency resolution with only three phase-locked loops. Low noise and low spurious are achieved by use of the fractional-N synthesis technique.

Fractional-N Loop 20-40 MHz Fine-Resolution Loop

MAY 1980 HEWLETT-PACKARD JOURNAL?

© Copr. 1949-1998 Hewlett-Packard Co.

tions and insights into the FDM measurement problem. Ron Tuttle, acting as co-project leader for the last year of the project, conducted most of the environmental and specifi cation compliance testing. The mechanical design with the innovative air distribution system was done by Mike Jewell. A special thanks goes to Mike Aken who followed the 3586A/B/C from the R&D lab to production engineering, thus insuring a smooth transition. Others on the project team include Tom Rodine, Mike Redig, Virgil Leenerts, Bob Atchley, Larry Sanders, Jerry Metz, Jerry Weibel, Steve Greer, Jon Pennington and Dave Deaver. References Rms-to-Dc Converter Linear Rms

Fig. to /Vi 80-dB range of input signal levels is compressed to 40 dB by this circuit arrangement so that a commercially available rms-to-dc converter can be used as an rms detector. The converter is economical and has both log and linear outputs.

overload detector. Here, there is no need for an 80-dB dynamic range, but there is a need to broaden the audio frequency range of the detector to accommodate the input RF range. This is done by incoherent sampling of the input waveform at an audio rate, feeding the stretched samples to the rms-to-dc converter. The statistics of the samples are the same as the statistics of a coherently sampled waveform but there is no need for the operator to be concerned with the sampling rate (if the sampling rate were a subharmonic of the signal frequency, the samples would represent the in stantaneous amplitude of the waveform at only one point on the waveform).4 Incoherent sampling is achieved by frequency-modulating the sampling rate.

1. J.R. Urquhart, "An Automatic Selective Level Measuring Set for Multichannel Communications Systems," Hewlett-Packard Jour nal, January 1976. 2. J.W. Daniels and R.L. Atchley, "A Precision Spectrum Analyzer for the lO-Hz-to-13-MHz Range," Hewlett-Packard Journal, May 1975. 3. D.D. Danielson and S.E. Froseth, "A Synthesized Signal Source with Journal, Generator Capabilities," Hewlett-Packard Journal, January 1979. 4. F.W. Wenninger, Jr., "A Sensitive New 1-GHz Sampling Volt meter with Unusual Capabilities," Hewlett-Packard Journal, July 1966.

Cool Operation

Cooling an instrument to assure long-term reliability al ways presents a problem if the instrument is to be compact and the use of a large, noisy fan is to be avoided. Quiet, cool operation was achieved for the 3586A/B/C by using the space between the motherboard and the gasketed bottom cover as a plenum chamber pressurized by the fan. The pressurized air is allowed to flow through holes in the motherboard, up past the circuit modules, through holes in the top of the card nest, and out the sides of the instrument. The sizes of the bleed holes were chosen according to the heat dissipated by the adjacent circuits so the higher-power circuits get more air. In this way, circuits do not get air that has already been warmed by circuits elsewhere in the in strument, and the airflow for each circuit is appropriate for the amount of heat dissipated. Also, since the cards are mounted vertically in the card nest, convection aids the air flow. This arrangement provides ample cooling of the in strument with the use of a quiet, low-power fan. Acknowledgments

As always with a complicated instrument like the 3586A/B/C, many people made contributions worthy of note. Cullen Darnell, who was engineering section manager for the earlier part of the project, provided many sugges

Paul L. Thomas Paul Thomas was born in Payson, Utah and attended Utah State University at Logan, graduating with a BSEE degree in 1965 and an MSEE degree in 1966. With HP's Loveland Instrument Division since 1966, he contributed to the de sign of the 675A/676A and 3570A Net work Analyzers and served as project leader for the 3571 A Tracking Spectrum Analyzer and the 3586A/B/C Selective Level Meter. There's a patent pending on the rms converter he de signed for the 3586. Paul is married, has ¿¿ three sons (ages 11, 14, and 17), and *,'* lives in Loveland, Colorado. An active outdoorsman who enjoys hunting, fishing, and hiking, he made the two fiberglass canoes that his family uses for fishing on many summer weekends. He also serves as a consultant for radio stations in the Loveland area.

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© Copr. 1949-1998 Hewlett-Packard Co.

Precision Synthesizer/Level Generator Has High Spectral Purity for Telecommunications Testing Use it alone oras a tracking signal source for the 3586A/BIC Selective Level Meter. Three versions meet CCITT, North American, and general-purpose requirements. by Phillip D. Winslow ON THE SURFACE, it might seem that testing a voice-grade telecommunications system would not require state-of-the-art source and analysis equipment. However, the problems incurred by stacking hundreds of amplifiers and multiplexing systems in cas cade make it necessary to use precision equipment to verify component performance within the error budgets required for system operation. Traditionally, FDM (frequency division multiplex) sys tems were tested by diverting traffic from part or all of the transmission channel and performing the required tests on the unloaded equipment. This approach provided a means of basic parameter testing with equipment that was scarcely more sophisticated than a wave analyzer and a tracking generator, but it suffered from the inefficiencies imposed by placing the equipment out of service. With the development of frequency synthesized analyz ers such as the HP 3745A Selective Level Measuring Set1 and more recently the HP 3 586A/B/C Selective Level Meter,2 some of the need for off-line testing has been eliminated by measurement techniques using existing pilot signals in the FDM system. With a new Synthesizer/Level Generator, Model 3336A/ B/C (Fig. 1), extensive in-service testing can now be per formed on FDM systems without causing transmission de gradation in voice or data channels. The 3336A/B/C's low

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Fig. 1. Model 3336A/B/C Synthesizer/Level Generator (3336C shown) generates precise frequencies and levels over a frequency range of 10 Hz to 20.999 999 999 MHz. Output levels are accurate within ±0.05 dB, and integrated phase noise is less than -60 dBc.

distortion, low spurious signal output, high amplitude ac curacy, and amplitude blanking feature (the output is sup pressed during frequency changes) make it fully capable of testing loaded systems. FDM Requirements

An FDM system is a hierarchy of multiplexing stages. The European CCITT system, for example, multiplexes twelve 4-kHz voice channels to form a group. Five groups are then multiplexed to form a supergroup. At the hypergroup level, 15 supergroups are multiplexed to yield a total of 900 voice channels. Depending on the bit rate required, data trans mission can be substituted for voice at the channel, group, or supergroup levels. In addition to the voice and data channels, pilot carriers are added at various points to serve as amplitude indicators and relocking signals. The FDM hardware is set up to insert and monitor test signals at each point in the multiplexing system and at various points in the amplifiers and radio links between multiplexers. One commonly performed test is frequency response. To make this test without interrupting transmis sion, a tone is inserted at the input port of the device under test. to test frequency is located between voice channels to avoid interference with information being transmitted. A narrow-band analyzer is used at the output port to measure the flatness of the output as the test signal is stepped in 4-kHz increments across the band of interest. Harmonic and spurious signals of the test generator must be down at least 50 dBc to avoid interference with informa tion channels or pilot signals that happen to coincide with a multiple of the test generator frequency. The output of the generator must be shut off or blanked when switching fre quencies to avoid sweeping through nearby channels. The amplitude transitions during blanking must be slow to avoid spectral splattering. The accuracy of frequency response and other measure ments depends on the reflection coefficient (return loss) of the source and analyzer. High return loss reduces stray reflections at test points, thereby reducing level inac curacies and imbalances in the internal system. Gain mea surements in FDM systems require a generator with good absolute accuracy in addition to flatness. Another commonly made measurement is adjacent channel noise with loading. A carrier is injected into a voice MAY 1980 HEWLETT-PACKARD JOURNALS

© Copr. 1949-1998 Hewlett-Packard Co.

Microprocessor

Keyboard and Display

HP-IB Input

Machine Data Bus (8 Bits)

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Sweep Output Circuits X-Drive I I I Z-Blank

External Reference Input

Marker

Fig. fractional-N The to Synthesizer/Level Generator uses the fractional-N synthesis technique to achieve controlled phase noise, low spurious outputs, and fast response. All operations are controlled by the Interface in response to commands from the front panel or the HP Interface Bus (ANSI/IEEE-488).

On Carrier Return Loss Measurement Return loss measurement of a conventional nonleveled source, even in the presence of the output signal', is a relatively straightfor ward test. A forward wave is launched by an excitation generator through a directional coupler towards the generator under test (see diagram). A spectrum analyzer at the output of the directional coupler detects the amplitude of the reflected wave. The excitation generator frequency is offset from that of the generator under test so the spec trum analyzer can distinguish the two signals. When on generator is leveled using a servo loop, return loss takes on a slightly different meaning. The loop action offers no improvement for offset frequencies outside the leveling loop bandwidth, and only a 6-dB passive inside the loop bandwidth. However, for passive loads, the effective output impedance depends almost entirely on the output matching resistor Zs, but the conventional technique for measuring return loss fails to give an answer that is a function of Z5 alone. When a small excitation signal is applied through the forward port of by directional bridge, a signal is developed at Vn given by Vn = A cos (c^t) + B cos (o)2t) + B cos (ci>3t) + B cos (o)2t) - B cos (2 and o>3 are sideband fre quencies. The leveling loop then generates AM sidebands on the output carrier that cancel the AM component (second line in above equation). The resultant net forward wave out of the generator can be expressed as V, = C cos (e^t) + D[(Zs-Z0)/(Zs+Z0)][cos (o>2t)+cos (u>3t)] + D[(Zs-Z0+Za)/(Zs+Z0+Za)][cos (o)2t)+cos (o>3t)] where C and D are amplitude constants. By using a peak detector instead of a spectrum analyzer, the AM portion alone (second line) is detected from the return port of the directional bridge and is propor tional to the reflection coefficient, from which the return loss can be calculated. -Phillip D. Winslow

Directional Bridge

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© Copr. 1949-1998 Hewlett-Packard Co.

channel with a test generator and the noise level in the adjacent channel is measured. The 33 36 A B C's 3-kHz adja cent channel noise specification of -72 dB allows wide dynamic range measurements to be made in this test. The inherently low phase noise of the 3336A/B/C also has an impact on data channel verification. Typically, a tone is inserted in the multiplex system and monitored at the end of the transmission channel with a phase jitter detector such as the HP 3586A/B/C. The phase jitter measurement is im plemented using a phase-locked loop phase detector and a 20-to-300-Hz bandpass filter. The floor of this measurement is in part set by the source's phase noise characteristic. The 3336A/B/C's phase noise specification translates to a low 0.3° peak-to-peak phase jitter.

ence between the two instruments lies in the output cir cuits. The 3325A has a function circuit designed to produce sine, square, and triangle waveforms. A de-coupled amplifier, optimized for minimum low-frequency distor tion and settling time, provides dc offset control. The 3336A/B/C uses an automatic leveling circuit to provide flatness and amplitude accuracy. An ac-coupled amplifier is used to provide low-distortion signals over the entire 21-MHz bandwidth. The 3336A and 3336B provide output impedances and connectors for use in the CCITT and Bell (North American) communications systems. The 3336C is designed for con ventional applications requiring only 50 and 75 ohm out puts.

Internal Structure

Leveling Loop

The block diagram of the 3336A/B/C Synthesizer/Level Generator, Fig. 2, is similar to that of the 3325A Synthesizer/Function Generator.3 The fractional-N circuits and mixer provide the same O-to-2 1-MHz driving signal with low noise and low spurious signal output. The differ-

One approach to a level generator design is to require the mixer, associated filters, and output amplifier to have very flat frequency response, precision gain, and high return loss. This approach can present formidable design and pro duction problems because of the accuracy and return loss required. The 3336A/B/C avoids these problems by sensing the output level near the attenuator and regulating it with control circuits. A fast leveling mode is provided for im proved response time at high output frequencies. Slow leveling is used at low frequencies and when settling time is not important. Fig. 3 shows conceptual block diagrams of the servo loop in slow and fast leveling modes. When the 3336A/B/C is in the slow leveling mode, the required accuracy and return loss are achieved with an automatic leveling control loop. The ac output of the amplifier is sensed and converted to a dc level by the rms detector and compared with a dc voltage generated by a processor-controlled digital-to-analog converter. Any error in amplitude introduced by the amplifier or offsets in the dc control circuits are detected and corrected by the com parator. The comparator is in effect an integrator and elimi nates any loop error resulting from finite gain. Since the output node is servoed to a constant ac voltage and is insensitive to load, it can be considered an accurate source with zero ohms output impedance. The addition of a series 50-ohm resistor results in a flat, accurate, and high-returnloss source. The rms converter consists of two thermally isolated heater-sensor pairs and a comparator (see page 12). The unknown ac voltage heats one pair, creating an imbalance that is sensed by the comparator. The comparator then drives the other pair into temperature balance by means of a dc voltage. Since the amounts of power dissipated in the two heater-sensor pairs are then equal, the dc voltage equals the rms value of the ac input voltage. This approach pro vides a means of detection that is insensitive to ambient temperature and accurate to high frequencies, but is rela tively slow in response. In fast leveling mode, another loop is placed inside the conventional loop described above. The inner loop is also a leveling loop, but uses a peak detector and different fre quency shaping to decrease settling time. As a result of the increased bandwidth, this loop serves to prelevel the signal before it is seen by the outer loop. The inner loop is seen by the outer loop as a modulatable source and the slow level ing function is preserved. The difference is that sudden

Output Block

Output Node

Output Block

DC Control

DC Reference (from Microprocessor Controlled DAC)

(b) Fig. 3. Conceptual block diagrams of the 3336A/B/C leveling loop in fast and slow leveling modes. Fast leveling, usable between 10 kHz and 21 MHz, gives ±0.15-dB flatness at sweep times as short as 0.03 second. Slow leveling can be used over the entire range of 10 Hz to 21 MHz. A front-panel button switches between the two modes.

MAY 1 980 HEWLETT-PACKARD JOURNAL 1 1

© Copr. 1949-1998 Hewlett-Packard Co.

A Monolithic Thermal Converter by Peter M. O'Neill The output leveling loop of the HP 3336A/B/C requires an accurate broadband amplitude detector to sense the actual output level. Two techniques are commonly used to measure ac voltages: peak and true-rms detection. Peak detectors have wider bandwidths but suffer from sensitivity to harmonics and absolute accuracy problems. There are two kinds of true-rms detectors. The analog computa tional kind uses functional blocks to execute the square, integration, and square root functions of the defining equation. It is inexpensive, but limited to low frequencies. Higher-frequency true-rms detectors require thermal techniques, which make use of the heating properties of ac and dc signals. Until recently, most such devices were expensive and bulky ther mocouples or hybrids. Now, integrated circuit technology has made possible a low-cost, broadband, monolithic silicon, thermal rms-todc converter.

used tracking, the heaters because of their excellent temperature tracking, stability, dielectric isolation, and high-frequency response. The only significant bandwidth limitation is the inductance of the bond wires connecting the heater to the package leads. Monolithic construction offers many advantages for this circuit. It is batch-fabricated and easily packaged. The small size and close proximity of the thermal masses results in good resistor and diode parameter matching while minimizing the effects of outside thermal gradients. Acknowledgments The concept and design of the device was originated by Norman Dillman of HP's Loveland Instrument Division, who also developed the silicon etching techniques and performed the system analysis.

Operation The thermal converter uses two heater/temperature-sensor pairs on separate thermally-isolated masses. An ac signal is applied to one heater resistor causing a rise in its temperature. A dc voltage is then fed back to a heater on an identical thermal mass until it produces a temperature equal to that of the first thermal mass as determined by a match in the temperature-sensor voltage outputs. The thermal time constants of the masses provide averaging, so that at equal voltages, the dc voltage driving one side equals the rms value of the ac voltage driving the other. The use of two sensors in a balanced configuration reduces the effects of common-mode sensor drift caused by ambient temperature and heater and sensor drift. Fig. 1 is a photograph of the converter. Design and Fabrication A novel feature of this thermal converter is the production of the entire Fig. structure within a single crystal chip of silicon (see Fig. 2). Together the anisotropically etched mass and its support form a single-pole thermal low-pass filter that performs the mean operation in determining the root-mean-square value. The filter determines the low-frequency operating limit of the device. The temperature sensors are high-stability junction diodes that have a voltage temperature coefficient of about -2 mV/°C when biased at constant current. Tantalum nitride thin-film resistors are

Fig. 2. Scanning electron micrograph of the back of the ther mal converter showing the anisotropically etched thermal structure.

Fig. 1. Top view of the HP thermal rms converter.

12 HEWLETT-PACKARD JOURNAL MAY 1980

© Copr. 1949-1998 Hewlett-Packard Co.

Peter M. O'Neill f /Pete O'Neill was born in Philadelphia, -J Pennsylvania and grew up in Wil mington, Delaware. He received his BSEE and MSEE degrees in 1977 and 1978 from Purdue University. Joining HP in 1 978 as an integrated circuit pro cess engineer, he completed de velopment of the fabrication process for the thermal rms converter used in the 3336A/B/C, and introduced it to pro duction. A member of IEEE, he lives in Loveland, Colorado and spends his spare time working on his new house, woodworking, skiing, bicycling, and teaching a junior high school religion class.

References 1 . J.R. Urquhart, "An Automatic Selective Level Measuring Set for Multichannel Communications Systems." Hewlett-Packard Jour nal. January 1976. 2. P.L. Thomas, this issue, page 3. 3. D.D. Danielson and S.E. Froseth, "A Synthesized Signal Source with Function Generator Capabilities." Hewlett-Packard Journal. January 1979.

Fig. 4. Slow and fast leveling loop responses to an output short-to-open transition.

errors in level caused by frequency or load changes are compensated more quickly by the inner loop. The outer loop only has to correct for slow drifts in the inner loop's characteristics. Fig. 4 shows fast and slow loop responses to a short at the output of the generator. The point monitored is the output node of the amplifier. Acknowledgments

Bill Spaulding was the original project manager. Market ing support was provided by David Ford, Bill Arrington and Paul Rumford. Norm Dillman, Bruce Huibregtse, and Pete O'Neill implemented the thermal converter. Art Dumont provided software with initial work done by Mike Price. Jim Freeman designed the mechanical portions of the instru ment. Special appreciation is expressed for the guidance and support of Doug Garde.

Phillip D. Winslow Phil Winslow joined HP's Loveland In strument Division in 1974 soon after graduating from California State Polytechnic University with a BSEE degree. He's contributed to the design of the 3335A Frequency Synthesizer and served as project manager for the 3336A/B/C Synthesizer/Level Generator. Born in Yuba City, California, Phil now lives in Loveland, Col orado. He's a skier and a classical guitarist, and his interests include pipe organs, baroque music, optical com munications, and high-fidelity systems.

SPECIFICATION SUMMARY HP Model 3586A/B/C Selective Level Meter FREQUENCY: RANGE: 50 Hz to 32 5 MHz ACCURACY • 10~5'yr< = 2 • 1 0 ~ 7,'yr optonall RESOLUTION: 0 1 Hz. COUNTER ACCURACY ± 1 0 Hz - 0 1 Hz

DYNAMIC RANGE: IMAGE REJECTION (100-132 MHz): -80 dBc IF REJECTION 15625 Hz. -80 dBc 50MHz. -60 dBc. SPURIOUS SIGNALS. >1600 Hz ottset. -SOdBc. 300 Hz to 1600 Hz offset, - 75 dBc DISTORTION Harmonics: - 70 dB below full scale, low distortion mode IM: -70 dB below lull scale, 200 Hz to 20 kHz offset 75 dB below full scale, 20 kHz to 1 MHz offset. HP-IB CONTROL: Compatible with ANSMEEE 48B-1978 OPTIONS:

SELECTIVITY: 3 dB Bandwrith ± 10%

•3100 Hz and WT D opi «na I ADJACENT CHANNEL REJECTION 75 d CARRIER REJECTION 60 dB PASSBAND FLATNESS -0 3 dB AMPLITUDE: RANGE. -2010 -120 dBm

AMPLITUDE: RANGE: 50fl: -71.23 to - 8 76 dBm 7511.60011 -72.9910 '1.00 dBm. 12411. 13511 -762310 >1 76dBm RESOLUTION 001 dB ACCURACY ±0.05dB.20rClo30 C.al 10 kHz iot 50. 75, 60011 outputs or 50 kHz lor 124, 135. 15011 outputs I -008 dBO to 55 C) FLATNESS ±0 1 dB (±0.07 Option 005), at full output ATTENUATOR ACCURACY iO.1 to = 0.3dBs!andafd. ~ 0.035 to ± 0 1 dBOptionOOS BLANKING Sot! blanking to - 85 dBm SPECTRAL PURITY: HARMONIC LEVELS 60 dB, 50 Hz lo 1 MHz. -55 ÜB. 1 MHz to 5 MHz. -50 dB, 5 MHz to 20.9 MHz PHASE NOISE Integrated. -64 dB. 30 kHz BW. SSB, -72 dB, 3 kHz BW, fc ±2 kHz. SPURIOUS: 70 dB down or 100 dBm ( 115 dBm with Option 005, depends on output and frequency) PHASE JITTER • ±03 p-p EXTERNAL MODULATION: AM. 50 Hz lo 50 kHz. 0 to lOO't. PM dc lo 5 KHz, 0 to r 850 PHASE OFFSET: - 719 9 versus arbitrary starling phase or 0'- relative FREQUENCY SWEEP: SWEEP RANGE Full range Of signal output SWEEP TIME. 001 s lo 99.9 s. depends on mode FLATNESS ±0 15 dB. (as! level, 003 s. HP-IB CONTROL: Compatible with ANSl'lEEE 488-1978 OPTIONS:

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Increased Versatility for a Versatile Logic State Analyzer During analysis of program flow in a computer system, dynamically qualified multiphase clocking enables the Model 1610B to acquire for display all parts of an asynchronous transaction while excluding irrelevant events. by Justin S. Merrill, Jr. and John D. Hansen HEWLETT-PACKARD'S most powerful logic state analyzer has been the Model 1610A, first introduced in 1 9 7 7. 1 With the specification of a series of program steps that must be encountered in proper order before data capture starts, this instrument can reach deep inside an executing program to capture a program sequence for analysis. The user can specify the number of times that each step must occur before the instrument starts looking for the next step so data capture can be directed to a particular branch or loop in a program. The 16 10 A can be selective about the data it captures — for example, only writes to an I/O port. It can also measure time intervals between specified program steps or count the number of program steps encountered in going from one specified event to another. New capabilities have now been added. These are found in a new version of the instrument known as the Model 1610B (Fig. 1). First among these new capabilities is mul

tiphase clocking. This means that events that do not occur simultaneously within a digital system's instruction cycle may be captured individually and then displayed together on the same line of the program listing. For example, many buses such as I/O buses found in minicomputers use a handshake protocol when transferring information. With a single-clock analyzer, only one portion of the total transaction — the address, for example — can be traced. The 1610B with its three clock inputs can use each of the hand shake signals to strobe the respective elements of the trans action into the analyzer and thereby trace the whole trans action (Fig. 2). Another capability new to the 1610B is "sequence protect on/off." As described earlier, the user can specify several steps (up to seven) that must be encountered in a program before the instrument starts to gather data, making it possi ble to restrict data capture to the desired leg of a branching program. Data acquisition does not begin until the last term

Fig. 1. Model 1610B Logic State Analyzer features multiphase clocking. Three clock inputs, each with four qualifiers, may be used to capture events in a digital system that do not occur simultaneously. A major application is decoding multiplexed buses.

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© Copr. 1949-1998 Hewlett-Packard Co.

TRACE

LIST

A LABEL OCT BASE SEQUENCE FOUND -17 824187 824118 -16 . .824111. -13 824112 -14 824113 -13 824114 -12 . .824115. -11 824116 -ia 824117 -89 824128 -88 . .824121. -87 824122 -86 824122 -89 824123 -84 . .824123. -83 824124 -82 824124 -81 024125 CENTER . .824121. +81 824122 +82

TRACE-COMPLETE

148883 162847 .828884. 858612 188881 828684 .148883. 871716 812858 823744 .818818. 818818 818818 851112 .851112. 852852 852852 157773 .818818. 818810

turned off, the sequence terms are not held in a protected part of memory and data is acquired continuously as the program executes with the earliest steps spilling off the top of the 64-word memory as later steps are entered at the bottom. In the END TRACE mode, data acquisition stops when the last sequence term is found. The 63 steps leading up to the last term are then retained for display. In the CENTER TRACE mode, the instrument continues to acquire data for 32 more steps, then stops with the 31 steps preced ing the last sequence term and the 32 steps following re tained for display. Thus in either case, the user is able to determine the steps leading up to the last sequence term. However, earlier sequence terms are not displayed unless they happen to fall among the steps retained for display. With sequence protect on, the 1610B functions identi cally to the 1610A. Double Buffering

Fig. 2. A 1610B display of addresses and the corresponding data occurring at different times on the same processor bus.

in the sequence is found, allowing time interval or program step counts to be made between sequence steps. This gives an overview of program operation on a macro level before specific information is obtained on a micro level in one area of code. Once a sequence term occurs, it is stored for the rest of the measurement in a protected part of memory for later dis play. There are times, however, when the user would want to see the specific program steps that lead up to the final sequence term, such as the words that lead to a trap. In this case, it would be preferable to abandon protection of the sequence terms for the sake of tracing where the trap came from. The 161 OB allows this tradeoff to be made. With the sequence protect function of the Model 1610B

To understand the multiple-clocking capabilities of the 1610B, let us examine how the analyzer's front end works. A block diagram is shown in Fig. 3. Data from buses or other signal lines in the digital system under test is applied to buffer registers, four lines per register. The data is entered into four of the registers (16 lines) by one clock (J), into two of them (8 lines) by a second clock (K), and into the remain ing two (8 lines) by a third clock (L). The last clock to occur is selected as the MASTER clock that transfers all the data in the 4-bit registers to the second-rank buffer storage regis ters. Thus, the instrument latches various portions of the input data in sequence as the clocks occur, and then the MASTER clock, the last one in the sequence, causes all the information to be transferred to the second rank where it is available for comparison to the trigger words and for trans fer to the display memory. The three clock inputs can be ORed together by the switches A and B shown in the diagram of Fig. 3. These are reed relays and thus have essentially zero propagation time and zero insertion loss. They are set open or closed at the

Clock J

To Analyzer

Clock L

Master Clock Delay

Fig. 3. Block diagram of the 161 OB front end. The last clock to occur is the MASTER clock that causes all the information in the first-rank register to be transferred to the second rank for analysis and display.

MAY 1980 HEWLETT-PACKARD JOURNAL 15

© Copr. 1949-1998 Hewlett-Packard Co.

*3 To Clock L, Master

8-Bit Byte »1 II 8-Bit Byte »2 II 8-Bit Byte -3

d>2 To Clock K

8-Bit Byte «4 II 8-Bit Byte "5 II 8-Bit Byte -6

«¿1 To Clock J Parallel Out

8-Bit Byte "7

Serial-ln Parallel-Out Shift Register High-Speed Clock

Fig. 4. To analyze systems that operate at higher clock rates than the 16WB's maximum rate, a circuit like this can be built by the user to obtain a three-phase low-speed clock from a high-speed clock (e.g., 10 MHz 3-phase from 30 MHz). Cau tion: This won't work if this circuit delays the clock so much that it occurs after the data is no longer valid.

time that the trace specifications are set up. With switches A and B closed, the analyzer functions as a 32-bit analyzer with a single-phase clock that latches the data on all 32 input lines at the same time. With A open and B closed, the analyzer functions as a 16-16-bit analyzer with 16 bits, say the address of an instruction, latched in by the J clock and the other 16 bits, say the instruction, latched by either the K or L clocks. Though occurring at different times, both address and instruction are acquired for display. With both A and B open, the 1610B functions in the 16-8-8 mode described earlier. The block diagram also shows two edge-triggered pulse generators for each clock. The enable inputs on the pulse generators determine whether each clock's positive edge, negative edge, both edges, or neither functions as the latch ing signal. These enable conditions are determined by bits stored in a RAM. Four qualifier inputs to the analyzer make up a 4-bit address that selects one of the bit patterns stored in the RAM. Thus, through the four qualifier lines, selection of the clocking signals can be under dynamic control of the digital program being monitored. For example, one can trace program flow on several buses simultaneously and use ancillary signals that identify reads, writes, DMAs, and so forth to exclude interrupts and DMAs without using any of the 32 data input lines to make this differentiation. Connections, 8080/1610B Pod 4 High-Order Addresses, A15-A8 Pod 3 Low-Order Addresses, A7-AO Pod 2 and 1 Both or Data Bus, D7-DO Using Part #5061-3613 Adapters Clock Pod Clock J and K to 02 using Part #5061-3613 Clock L to 01 Qual 3 DBIN Qual 2 WR Qual 1 Sync Qual O No Connection

Note: Pod 1 lines for label F displayed in order are: M E M R I M P M O U T H L T A S T A C K These are the status lines of the 8080.

W O

Fig. 5. Data display using triple probing. A threefold increase in frequency can be obtained in this way, at the expense of narrowing the effective analyzer word width.

Besides making it possible to capture and display the sequential steps of a handshake transaction simultane ously, the multiphase clocking will be especially useful for monitoring the newer microprocessors that use multi plexed buses. In several of these microprocessors, the ad dress bus is used at different times as the data bus. Multi phase clocking enables both the address and the data in volved in a transaction to be captured for display on the same program line. Another capability provided by multiphase clocking is operation at two or three times the analyzer's normal maximum clock rate, specifically operation at 20 or 30 MHz, though with reduced word width. This is done by double or triple probing of the data lines and deriving a multiphase clock. For example, the circuit of Fig. 4 can be built by the user to obtain a 10-MHz 3-phase clock from a 30-MHz clock. The acquired data would then be displayed as shown in Fig. 5.

Stop and List

Another refinement found in the 1610B is the "stop and list" mode. In the 1610A, data in the high-speed acquisition memory is transferred to the display memory only when the trace point is found and the high-speed memory is filled. In the 1610B, if the loss of the system clock suspends opera tion of the system under test before the data acquisition memory is filled or a trace point is found, the user can transfer the data for display by holding down the STOP key Format Specification Menu, 8080/1610B

C L O C K

. P O D

CLOCK QUALIFIERS < I , 0, X >

< J,K,L>

CLOCK POD PROBE

7

CLOCK J CLOCK K CLOCK L P 0 0 4 P 0 0 3 P O D 2 P O D I A 7 a 7 a 7 a

INTA

Fig. 6. Hard-to-capture OB setup and connections to monitor the 8080 microprocessor. Hard-to-capture 8080 status bits are easily captured and displayed with this setup.

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Connections. 8065,16108 Pod 4 High-Order Address A8-A 15 Pod 3 and 2 Low-Order Address-Data ADO-AD7 with adapter P o d 1 S 1 S O I O / M R D W R S T D 6 5 7 4 3 2 Clock Pod

Clock J ALE Clock K _RD Qual 3 IO/M Qual 1 SO

Format Specification Menu 8085 1610B

SID

Clock L WR Qual 2 S1 Qual O No Connection

Fig. with connections 8085 microprocessor multiplexes part of the address with the data. The connections and setup shown allow the 1610B to monitor the 8085.

for more than two seconds. The memory contents are then displayed with the title line reading: HISTORY AT STOP. This technique is also useful for determining what the data is doing when the analyzer fails to find the trace point.

tion on the status lines allows selection of the machine cycles of interest, as shown in the table below. The only one not recognized is INA, which requires a clock change. 8085 Machine Cycle Chart

Demultiplexing on Common Processors

Here are three examples of the use of the 1610B's multiple-phase qualified clocks for monitoring widely used processors. 8080. The 8080 is not usually thought of as a multiplexed processor, yet important information about each instruc tion cycle is contained in the status word that is multi plexed on the data bus at the beginning of each cycle. In many systems these status bits are difficult to get at or are only partially captured. Using a 1610B as shown in Fig. 6, the full status word can be captured and displayed. Storage qualification on this field allows the user to limit data capture to only interrupt acknowledge cycles, only stack operations, or only instruction fetches. Using the additional qualification available on the clocks, only reads or only writes on the bus can be selected. 8085. Instead of multiplexing the status bits, the 8085 mul tiplexes part of the address with the data. With the 1610B, the address can be entered, together with data, status, and control lines to specify the acquisition criteria. Qualifica Connections, LSI-11 Q-Bus 1610B Pod 4, 2 High-Order Address/Data BDAL15 - BDAL8 Pod 3, 1 Low-Order Address/Data BDAL7 - BDALO Clock Pod Clock J BSYNC (Address)(-) Clock K BDIN (Read Data)(+) Clock L BDOUT (Write Data)(+) For DMA Clock K or L Qual 3 BSACK For INT Vector Clock K or L Qual 2 BIAK Qual 3 No Connection Qual 4 No Connection

Machine Cycle Status

Control

IO/M Si SO O P C O D E F E T C H ( O F ) 0 1 1 M E M O R Y R E A D ( M R ) 0 1 0 M E M O R Y W R I T E ( M W ) 0 0 1 I / O R E A D ( I O R ) 1 1 0 I / O W R I T E ( I O W ) 1 0 1 ACKNOWLEDGE O F I N T R ( I N A ) , 1 1 1 B U S I D L E ( B I ) D A D 0 1 0 ACK.OF R S T . T R A P 1 1 1 H A L T T S 0 0 TS =High Impedance State

Fig. 7 shows how the 1610B can be set up to monitor the 8085. LSI-11. The LSI-11 Q-Bus is an 18-bit, asynchronous bus with data and address multiplexed. Data width is 16 •Intel Component Data Catalog. 1980. "Registered trademark. Digital Equipment Corporation.

Format Specification Menu LSI-11 Q-Bus 1610B

Fig. Corporation's 76706 setup and connections to monitor Digital Equipment Corporation's LSI- 1 1 Q-Bus, an 18-bit asynchronous bus with addresses and data multiplexed.

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© Copr. 1949-1998 Hewlett-Packard Co.

bits, with two status bits for errors. If the address is re stricted to 16 bits, the 32-bit width of the 1610B can follow the machine flow. Edges of the handshake lines can be used to clock in the address and data. The upper two bits of address are lost, but if these are important, they can be exchanged with the two lower bits. For DMA operation only, or for DMA exclusion, the BSACK signal on Qualifier 3 can be used on clocks K and L. For including or excluding interrupts, the BIAK signal on Qualifier 2 can be used on clocks K and L. The interrupt-acknowledge vector is in the data field with the same address as the preceding read or write. Fig. 8 shows a 1610B setup for monitoring the LSI-11 Q-Bus. John D. Hansen John Hansen received his BSEE and MSEE degrees from Brigham Young University in 1976 and 1977. With HP since 1977, he developed the acquisi tion hardware and a new power supply for the 161 OB Logic State Analyzer. He's a member of IEEE. Before coming to HP he served briefly as a UNESCO consultant in Rumania. A native of Richfield, Utah, John is married, has a son, and lives in Colorado Springs. He's active in his church, advises an Explorer Scout troop, owns two touring motorcycles, sings in choral groups, plays harmonica, and likes to cook.

Acknowledgments

There were many contributors to the project. The primary ones were Mike Davis as section manager, Rick Nygaard and Chris Jones for software, and Dan Kolody for marketing support. The mechanical design was done by Bobby J. Self.

Justin S. Merrill, Jr. W ~ ~ Justin Morrill has been developing logic analysis products for HP since 1972; IfeL — • one major patent has resulted from that •Mr work. Justin was project leader for the 161 OB Logic State Analyzer and is now a group leader in the logic analysis ..¿r.; laboratory. He's a member of ACM. Born in Lawton, Oklahoma, Justin grew up in Houston, Texas. After serving in the U.S. Army for three years, he at tended Cornell and Rice Universities, receiving BS and MS degrees in elec trical engineering from Rice in 1 971 and 1972. He now lives in Cascade, Col orado, where he's leader of the medical rescue squad and a volunteer fireman. He's married, has two chil dren, and enjoys backpacking and cross country skiing.

SPECIFICATIONS HP Models 1610A/B Logic State Analyzers Clock and Data Input REPETITION RATE: to 10 MHz. INPUT RC: 50 k!i shunted by «1 4 pF at the probe tip; (10248C) 1 00 kil shunted by «1 4 pF at the probe tip. INPUT BIAS CURRENT: «20 /¿A. INPUT THRESHOLD: TTL, fixed at approx +1.5V; variable, ±10 Vdc. MAXIMUM INPUT: -15 V to +15 V. MINIMUM INPUT SWING: 0.5 V. CLOCK PULSE WIDTH: 20 ns at threshold level. EDGE-TO-EDGE TIMING: (1610B) master active edge to master active edge, 100 ns; master slave edge to next slave active edge, 20 ns; slave active edge to next slave or master active edge, zero. DATA SETUP TIME: time data and clock qualifiers must be present and stable prior to active clock transition, 20 ns. HOLD stable time data and clock qualifiers must be present and stable after active clock transition, zero.

Trigger and Measurement Enable Outputs TRIGGER OUTPUT (rear panel): A 50 ns ±10 ns positive TTL level trigger pulse is gener ated position time the trace position is recognized. If the trace position includes a word se quence, occur pulse occurs when the last word is found. Trigger outputs continue to occur each time the trigger conditions are met until a new specification is traced or the Stop key is pressed. Pulse rep-rate is 0 to 10 MHz depending on the input data rates. In continuous or compared trace modes, the internal display process blanks out pulses for 100 ps at rep rates of